In setting the clock interval to a value well above the worst-case propagation delay, it is possible to design the whole CPU and the way in which it strikes information around the “edges” of the rising and falling clock sign. This has the benefit of simplifying the CPU significantly, each from a design perspective and a element-rely perspective. However, it also carries the drawback that the complete CPU must wait on its slowest parts, even though some parts of it are much quicker. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see beneath).
Pipelining does, nevertheless, introduce the likelihood for a situation the place the results of the earlier operation is required to complete the following operation; a situation usually termed information dependency battle. To cope with this, further care have to be taken to examine for these types of conditions and delay a … Read More